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Synopsys UALink IP Solution for Next-Gen AI Infrastructures

Discover the Synopsys UALink IP Solution, powered by silicon-proven 200G PHY IP and backed by decades of SerDes expertise. This complete solution—featuring controller, PHY, and verification IP—delivers low-latency, high-bandwidth connectivity to support systems with up to 1,024 AI accelerators, enabling scalable and efficient AI and HPC infrastructures. Watch now to learn more.

Synopsys joined the UALink Consortium to address the evolving needs of our customers in AI and HPC markets. As a leader in high-performance interface IP solutions, we are committed to enabling open, scalable, and efficient systems that are critical for next-generation AI workloads. By participating as a Promoter member, we aim to contribute in the development of UALink technology and to the creation of open industry standards that foster innovation and collaboration. This aligns with our mission to provide cutting-edge solutions that empower our customers to achieve their goals efficiently and effectively.

UALink technology is vital for enabling high-speed, low-latency interconnects tailored to AI workloads. It enhances existing standards like Ethernet and PCIe, optimizing performance for tasks such as inference and generative AI. For Synopsys, UALink aligns with our silicon-proven IP portfolio, supporting up to 200 Gbps per lane, helping customers build scalable, high-performance systems efficiently.