Our latest webinar featured Consortium members Nathan Kalyanasundharam (AMD), Chris Petersen (Astera Labs), and Peter Onufryk (Intel) providing an overview of the UALink 200G 1.0 Specification, highlighting how the specification defines a low-latency, high-bandwidth interconnect with native memory semantics for communication between accelerators and switches in AI computing pods.
The audience was incredibly engaged and posed several questions to the panel. As time was limited and the questions were plentiful, we were unable to address them all in real time. To continue the conversation, our group of panelists has provided responses to the questions below.
If you were not able to attend the live webinar, the recording is now available via YouTube, and the presentation slides can be downloaded from the UALink Consortium website.
We are interested in hearing your thoughts and fielding any questions you may have. Please contact us at press@ualinkconsortium.org with feedback and to continue this conversation.
Webinar Q&A
Q: Does UALink plan to support larger load and store operations (e.g., 256/512 vs 64 byte)?
A: Yes. UALink supports 64B/128B/192B/256B length requests. The maximum length is 256B, as most accelerators interleave high bandwidth memory at a 256B boundary. It is also important to note that single-copy atomicity on stores is harder to guarantee when the store spans multiple memory channels.
Q: What’s the target port-to-port latency of a UALink Switch?
A: Port-to-port latency is based on implementation, port speed, and switch scale. At a high level, with 400G ports, a 25T switch is <= 150 ns, 50T <200ns, and a 100T switch < 250ns.
Q: Do you anticipate UALink supporting optical in the 2.0 specification? If so, would it also go over fiber?
A: UALink does not currently have plans to specify optical requirements. However, developers can use 200G signaling for optics implementations.
Q: Are there plans to conduct interoperability testing for solutions from different providers?
A: The UALink Compliance Specification is currently in development, with interoperability testing expected to be facilitated by the Consortium.
Q: Why does the UALink 200G 1.0 spec limit the UALink port to 800G (4x200G) instead of 1.6T(8x200G)?
A: UALink supports 800G port, 2x 400G ports, or 4x 200G ports. The reason for limiting the max port bandwidth to 100GBytes/s is to ease implementations.
Q: Why did UALink choose to provide PCIe® as an alternative PHY to the current Ethernet?
A: Several UALink members have designs featuring 128 G-capable PHY. This provides higher bandwidth than 100G Ethernet, and we have found that some customers prefer the flexibility of using the port as a PCIeG7 or UAL128.
Q: Can UALink technology replace the PCIe PHY between the CPU and the Accelerator?
A: This is not the Consortium’s current focus. PCIe is required for device enumeration, address translation, secure execution (TEE/TDISP), and many other services.
Q: Does the UALink specification define the maximum latency and minimum bandwidth for each interface (PHY/DL/Transceivers)?
A: It does not.